A number of configurations in computer memory exist to protect data against errors or failure of memory devices. Error Check and Correcting (ECC) configurations such as Chipkill™ exist that protect computer memory systems from any single memory chip failure as well as multi-bit errors from any portion of a single memory chip. In Chipkill™, bits of multiple ECC words are scattered across multiple memory chips, such that the failure of any one memory chip will affect each ECC value looking like multiple correctable errors. This allows memory contents to be reconstructed despite the complete failure of one chip. ECC implementations more complex than Chipkill™ are seldom done with most current high density memory integrated circuits because of the additional memory and chip area required. Simpler detection/correction schemes such as parity check or single bit correction are often implemented.
In computer hard drive memory, Redundant Arrays of Inexpensive Disks (RAID) configurations allow backup of data when multiple drives are arranged in parallel, where n+1 drives are used to store data. The extra memory of the “1” drive of n+1 in a RAID 4 or RAID 5 configuration is used to store the ECC data. However, RAID configurations are often relatively slow during write operations because each write requires updating of the ECC data, such that two writes are required for every operation (one for the data being written, and another for the updated ECC being written). Performance of a RAID 5 configuration when writing is approximately one half the performance of reading. Other operations of a parallel RAID configuration, such as data recovery, can be much slower than half the speed of a read operation.
The inventor has realized that improved memory configurations with error recovery are desired that reduce the amount of memory needed to store error recover data (e.g., ECC data) for cases where recovery from failures of memory components is required. The inventor has further realized that improved memory configurations with error recovery are desired that reduce any impact to operating speed during error recovery, data write operations, etc. The inventor has further realized that memory configurations are desired that allow ECC to be included or left out without needing differing kinds of components, or adding expense if ECC is not required.